View AT80C51RD2-SLRUM_4189116.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

features ? 80c52 compatible ? four 8-bit i/o ports ? three 16-bit timer/counters ? 256 bytes scratch pad ram ? 8 interrupt so urces with 4 priority levels ? dual data pointer ? variable length movx for slow ram/peripherals ? high-speed architecture ? 10 to 40 mhz in standard mode ? 16k/32k bytes on-chip rom program ? at80c51rd2 romless versions ? on-chip 1024 bytes expanded ram (xram) ? software selectable size (0, 256, 512, 768, 1024 bytes) ? 256 bytes selected at reset ? keyboard interrupt in terface on port p1 ? 8-bit clock prescaler ? 64k program and data memory spaces ? improved x2 mode with independant selection for cpu and each peripheral ? programmable counter array 5 channels with: ? high-speed output ? compare/capture ? pulse width modulator ? watchdog timer capabilities ? asynchronous port reset ? full duplex enhanced uart ? dedicated baud rate generator for uart ? low emi (inhibit ale) ? hardware watchdog timer (one -time enabled with reset-out) ? power control modes ?idle mode ? power-down mode ?power-off flag ? power supply: 2.7v to 5.5v ? temperature ranges: commercial (0 to +70 c) and industrial (-40 c to +85 c) ? packages: pdil40, plcc44, vqfp44 80c51 high performance rom 8-bit microcontroller at80c51rd2
2 4113d?8051?01/09 at80c51rd2 1. description at80c51rd2 microcontrollers are high per formance versions of the 80c51 8-bit microcontrollers. the microcontrollers retain all features of the atmel 80c52 with 256 bytes of internal ram, a 7- source 4-level interrupt controller and three timer/counters. in addition, the microcontrollers have a programmable counter array, an xram of 1024 byte, a hardware watchdog timer, a keyboa rd interface, a more versatile serial channel that facilitates multiprocessor communication (euart) and a speed improvement mechanism (x2 mode). the microcontrollers have 2 software-selectable mo des of reduced activity and 8 bit clock pres- caler for further reduction in power consumption. in idle mode, the cpu is frozen while the peripherals and the inte rrupt system are still operating. in the power-down mode, the ram is saved and all other functions are inoperative. table 1. memory size 2. block diagram notes: 1. alternate function of port 1 2. alternate function of port 3 rom (bytes) xram (bytes) total ram (bytes) i/o at80c51rd2 romless 1024 1280 32 timer 0 int ram 256x8 t0 t1 rxd txd wr rd ea psen ale/ xtal2 xtal1 euart cpu timer 1 int1 ctrl int0 (2) (2) c51 core (2) (2) (2) (2) port 0 p0 port 1 port 2 port 3 parallel i/o ports & ext. bus p1 p2 p3 xram 1kx8 ib-bus pca reset prog watch dog pca eci vss vcc (2) (2) (1) (1) timer2 t2ex t2 (1) (1) key board + brg
3 4113d?8051?01/09 at80c51rd2 3. pin configurations p1.7cex4 p1.4/cex1 rst p3.0/rxd p3.1/txd p1.3cex0 1 p1.5/cex2 p1.6/cex3 p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 p3.6/wr p3.7/rd xtal2 xtal1 vss p2.0/ad8 p2.1/ad9 p2.2/ad10 p2.3/ad11 p2.4/ad12 p0.4/ad4 p0.6/ad6 p0.5/ad5 p0.7/ad7 ale/prog psen ea p2.7/ad15 p2.5/ad13 p2.6/ad14 p1.0/t2 p1.2/eci p1.1/t2ex vcc p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 pdil40 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 43 42 41 40 39 44 38 37 36 35 34 p1.4/cex1 p1.0/t2 p1.1/t2ex p1.3/cex0 p1.2/eci nic* vcc p0.0/ad0 p0.2/ad2 p0.3/ad3 p0.1/ad1 p0.4/ad4 p0.6/ad6 p0.5/ad5 p0.7/ad7 ale/prog psen ea nic* p2.7/a15 p2.5/a13 p2.6/a14 p1.5/cex2 p1.6/cex3 p1.7/cex4 rst p3.0/rxd nic* p3.1/txd p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 p3.6/wr p3.7/rd xtal2 xtal1 vss p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 nic* 12 13 17 16 15 14 20 19 18 21 22 33 32 31 30 29 28 27 26 25 24 23 vqfp44 1.4 1 2 3 4 5 6 7 8 9 10 11 18 19 23 22 21 20 26 25 24 27 28 5 4 3 2 1 6 44 43 42 41 40 p1.4/cex1 p1.0/t2 p1.1/t2ex p1.3/cex0 p1.2/eci nic* vcc p0.0/ad0 p0.2/ad2 p0.1/ad1 p0.4/ad4 p0.6/ad6 p0.5/ad5 p0.7/ad7 ale/prog psen ea nic* p2.7/a15 p2.5/a13 p2.6/a14 p3.6/wr p3.7/rd xtal2 xtal1 vss p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p1.5/cex2 p1.6/cex3 p1.7/cex4 rst p3.0/rxd nic* p3.1/txd p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 p0.3/ad3 nic* 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 plcc44 *nic: no internal connection
4 4113d?8051?01/09 at80c51rd2 table 3-1. pin description mnemonic pin number type name and function dil plcc44 vqfp44 1.4 v ss 20 22 16 i ground: 0v reference v cc 40 44 38 i power supply: this is the power supply voltage for normal, idle and power-down operation p0.0 - p0.7 39 - 32 43 - 36 37 - 30 i/o port 0 : port 0 is an open-drain, bi-directional i/o port. port 0 pins that have 1s written to them float and can be used as high impedance inputs. port 0 must be polarized to v cc or v ss in order to prevent any parasi tic current consumption. port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. in this application, it uses strong internal pull-up when emitting 1s. port 0 also inputs the code bytes during eprom programming. external pull-ups are requi red during program verification during which p0 outputs the code bytes. p1.0 - p1.7 1 - 8 2 - 9 40 - 44 1 - 3 i/o port 1: port 1 is an 8-bit bi-directional i/o po rt with internal pull-ups. port 1 pins that have 1s written to them are pull ed high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins t hat are externally pulled low will source current because of the internal pull-ups. po rt 1 also receives the low-order address byte during memory programming and verification. alternate functions for t89c51rb2/rc2 port 1 include: 1 2 40 i/o p1.0 : input/output i/o t2 (p1.0): timer/counter 2 external count input/clockout 2 3 41 i/o p1.1: input/output i t2ex: timer/counter 2 reload/capture/direction control 3 4 42 i/o p1.2: input/output i eci: external clock for the pca 4 5 43 i/o p1.3: input/output i/o cex0: capture/compare external i/o for pca module 0 5 6 44 i/o p1.4: input/output i/o cex1: capture/compare external i/o for pca module 1 6 7 1 i/o p1.5: input/output i/o cex2: capture/compare external i/o for pca module 2 7 8 2 i/o p1.6: input/output i/o cex3: capture/compare external i/o for pca module 3 8 9 3 i/o p1.7: input/output: i/o cex4: capture/compare external i/o for pca module 4 xtal1 19 21 15 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator circuits. xtal2 18 20 14 o crystal 2: output from the inverting oscillator amplifier
5 4113d?8051?01/09 at80c51rd2 p2.0 - p2.7 21 - 28 24 - 31 18 - 25 i/o port 2 : port 2 is an 8-bit bi-directional i/o port with internal pull-ups. port 2 pins that have 1s written to them are pull ed high by the internal pull-ups and can be used as inputs. as inputs, port 2 pins t hat are externally pulled low will source current because of the internal pull-ups. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (m ovx @dptr). in this application, it uses strong internal pull-ups emitting 1s. during accesses to external data memory that use 8-bit addresses (movx @ri), port 2 emits the contents of the p2 sfr. some port 2 pins receive the high order address bits during rom reading and verification: p2.0 to p2.5 for 16 kb devices p2.0 to p2.6 for 32 kb devices p3.0 - p3.7 10 - 17 11, 13 - 19 5, 7 - 13 i/o port 3: port 3 is an 8-bit bi-directional i/o po rt with internal pull-ups. port 3 pins that have 1s written to them are pull ed high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins t hat are externally pulled low will source current because of the internal pull-ups. port 3 also serves the special features of the 80c51 family, as listed below. 10 11 5 i rxd (p3.0): serial input port 11 13 7 o txd (p3.1): serial output port 12 14 8 i int0 (p3.2): external interrupt 0 13 15 9 i int1 (p3.3): external interrupt 1 14 16 10 i t0 (p3.4): timer 0 external input 15 17 11 i t1 (p3.5): timer 1 external input 16 18 12 o wr (p3.6): external data memory write strobe 17 19 13 o rd (p3.7): external data memory read strobe rst 9 10 4 i/o reset: a high on this pin for two machine cycl es while the oscill ator is running, resets the device. an internal diffused resistor to v ss permits a power-on reset using only an external capacitor to v cc . this pin is an output when the hardware watchdog forces a system reset. ale/prog 30 33 27 o (i) address latch enable/program pulse: output pulse for latching the low byte of the address during an access to external memory. in normal operation, ale is emitted at a constant rate of 1/6 (1/3 in x2 mode) the osci llator frequency, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. this pin is also the program pulse input (prog ) during flash programming. ale can be disabled by setting sfr?s auxr.0 bit. with this bit set, ale will be inactive during internal fetches. psen 29 32 26 o program strobe enable: the read strobe to external program memory. when executing code from the external program memory, psen is activated twice each machine cycle, except that two psen activations are ski pped during each access to external data memory. psen is not activated during fetches from internal program memory. ea 31 35 29 i external access enable: ea must be externally held low to enable the device to fetch code from external program memory locations. if security level 1 is programmed, ea will be internally latched on reset. table 3-1. pin description (continued) mnemonic pin number type name and function dil plcc44 vqfp44 1.4
6 4113d?8051?01/09 at80c51rd2 4. sfr mapping the special function registers (sfrs) of the micr ocontroller fall into t he following categories: ? c51 core registers: acc, b, dph, dpl, psw, sp ? i/o port registers: p0, p1, p2, p3 ? timer registers: t2con, t2mo d, tcon, th0, th1, th2, tmod, tl0, tl1, tl2, rcap2l, rcap2h ? serial i/o port registers: saddr, saden, sbuf, scon ? pca (programmable counter array) re gisters: ccon, ccapm x, cl, ch, ccapxh, ccapxl (x: 0 to 4) ? power and clock control registers: pcon ? hardware watchdog timer registers: wdtrst, wdtprg ? interrupt system registers: ie0, ipl0, iph0, ie1, ipl1, iph1 ? keyboard interface re gisters: kbe, kbf, kbls ? brg (baud rate generator) registers: brl, bdrcon ? clock prescaler register: ckrl ? others: auxr, auxr1, ckcon0, ckcon1
7 4113d?8051?01/09 at80c51rd2 table 3 shows all sfrs with their address and their reset value. table 4-1. sfr mapping bit addressable non-bit addressable 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8h ch 0000 0000 ccap0h xxxx xxxx ccap1h xxxx xxxx ccapl2h xxxx xxxx ccapl3h xxxx xxxx ccapl4h xxxx xxxx ffh f0h b 0000 0000 f7h e8h cl 0000 0000 ccap0l xxxx xxxx ccap1l xxxx xxxx ccapl2l xxxx xxxx ccapl3l xxxx xxxx ccapl4l xxxx xxxx efh e0h acc 0000 0000 e7h d8h ccon 00x0 0000 cmod 00xx x000 ccapm0 x000 0000 ccapm1 x000 0000 ccapm2 x000 0000 ccapm3 x000 0000 ccapm4 x000 0000 dfh d0h psw 0000 0000 d7h c8h t2con 0000 0000 t2mod xxxx xx00 rcap2l 0000 0000 rcap2h 0000 0000 tl2 0000 0000 th2 0000 0000 cfh c0h c7h b8h ipl0 x000 000 saden 0000 0000 bfh b0h p3 1111 1111 ie1 xxxx xxx0b ipl1 xxxx xxx0b iph1 xxxx xxx0b iph0 x000 0000 b7h a8h ie0 0000 0000 saddr 0000 0000 afh a0h p2 1111 1111 auxr1 xxxx xxx0 wdtrst xxxx xxxx wdtprg xxxx x000 a7h 98h scon 0000 0000 sbuf xxxx xxxx brl 0000 0000 bdrcon xxx0 0000 kbls 0000 0000 kbe 0000 0000 kbf 0000 0000 9fh 90h p1 1111 1111 ckrl 1111 1111 97h 88h tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 auxr xx0x 0000 ckcon0 0000 0000 8fh 80h p0 1111 1111 sp 0000 0111 dpl 0000 0000 dph 0000 0000 pcon 00x1 0000 87h 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f reserved
8 4113d?8051?01/09 at80c51rd2 5. oscillators 5.1 overview one oscillator is available for cpu: ? osc used for high frequency (3 mhz to 40 mhz) in order to optimize the power consumption and the execution time needed for a specific task, an internal prescaler feature has been implemented between the selected oscillator and the cpu. 5.2 registers table 5-1. clock reload register reset value = 1111 1111b not bit addressable 5.2.1 prescaler divider a hardware reset puts the prescaler divider in the following state: ? ckrl = ffh: f clk cpu = f clk periph = f osc /2 (standard c51 feature) ks signal selects osc: f clk out = f osc ? any value between ffh down to 00h can be written by software into ckrl register in order to divide frequency of th e selected oscillator: ? ckrl = 00h: minimum frequency f clk cpu = f clk periph = f osc /1020 (standard mode) f clk cpu = f clk periph = f osc /510 (x2 mode) ? ckrl = ffh: maximum frequency f clk cpu = f clk periph = f osc /2 (standard mode) f clk cpu = f clk periph = f osc (x2 mode) ?f clk cpu and f clk periph in x2 mode: in x1 mode: 76543210 -------- bit number bit mnemonic description 7:0 ckrl clock reload register: prescaler value f cpu f = clkperiph f osc 2 255 ckrl ? () ---------------------------------------------- = f cpu f = clkperiph f osca 4255 ckrl ? () ---------------------------------------------- =
9 4113d?8051?01/09 at80c51rd2 6. enhanced features in comparison to the original 80c52, the microcontrollers implement the following new features: ? x2 option ? dual data pointer ? extended ram ? programmable counter array (pca) ? hardware watchdog ? 4-level interrupt priority system ? power-off flag ? power on reset ? once mode ? ale disabling ? some enhanced features are also located in the uart and the timer 2 6.1 x2 feature and osc clock generation the microcontroller core needs only 6 clock periods per machine cycle. this feature called ?x2? provides the following advantages: ? divides frequency crystals by 2 (cheaper crystals) while keeping same cpu power. ? saves power consumption while keeping sa me cpu power (oscillator power saving). ? saves power consumption by dividing dynamica lly the operating frequency by 2 in operating and idle modes. ? increases cpu power by 2 while keeping same crystal frequency. in order to keep the or iginal c51 compatibility, a divider by 2 is inserted between the xtal1 sig- nal and the main clock input of the core (phas e generator). this divider may be disabled by software. 6.1.1 description the clock for the whole circuit and peripherals is first divided by two before being used by the cpu core and the peripherals. this allows any cyclic ratio to be accepted on xtal1 input. in x2 mode, as this divider is bypassed, the signals on xtal1 must have a cyclic ratio between 40 to 60%. figure 6-1 shows the clock generation block diagram . x2 bit is validated on the rising edge of the xtal1 2 to avoid glitches when switching from x2 to standard mode. figure 6-2 shows the switching mode waveforms. figure 6-1. clock generation diagram xtal1 2 ckcon0 x2 8-bit prescaler f osc f xtal 0 1 xtal1:2 ckrl clk periph clk cpu idle
10 4113d?8051?01/09 at80c51rd2 figure 6-2. mode switching waveforms the x2 bit in the ckcon0 register (see table 6 -1) allows to switch from 12 clock periods per instruction to 6 clock periods and vice versa. at reset, the speed is set according to x2 bit of hardware config byte (hcb). by default, standard mode is activated. setting the x2 bit acti- vates the x2 feature (x2 mode). the t0x2, t1x2, t2x2, uartx2, pcax2 and wdx2 bits in the ckcon0 register ( table 6-1 ) allow to switch from st andard peripheral speed (12 clock periods per peripheral clock cycle) to fast peripheral speed (6 clock periods per peripheral clock cycle). these bits are active only in x2 mode. table 6-1. ckcon0 register ckcon0 - clock control register (8fh) xtal1:2 cpu block x2 bit x2 mode std mode std mode f osc xtal1 76543210 - wdx2 pcax2 six2 t2x2 t1x2 t0x2 x2 bit number bit mnemonic description 7- reserved do not set this bit. 6wdx2 watchdog clock (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect). cleared to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle.
11 4113d?8051?01/09 at80c51rd2 reset value = 0000 000?hcb.x2?b (see hardware config byte) not bit addressable 5 pcax2 programmable counter array clock (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect). cleared to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 4six2 enhanced uart clock (mode 0 and 2) (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect). cleared to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 3t2x2 timer 2 clock (this control bit is validated when t he cpu clock x2 is set; when x2 is low, this bit has no effect). cleared to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 2t1x2 timer 1 clock (this control bit is validated when t he cpu clock x2 is set; when x2 is low, this bit has no effect). cleared to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle 1t0x2 timer 0 clock (this control bit is validated when t he cpu clock x2 is set; when x2 is low, this bit has no effect). cleared to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle 0x2 cpu clock cleared to select 12 clock periods per ma chine cycle (std mode) for cpu and all the peripherals. set to select 6clock periods per machine cycle (x2 mode) and to enable the individual peripherals "x2" bits. programmed by hardware after power-up regar ding hardware config byte (hcb). bit number bit mnemonic description
12 4113d?8051?01/09 at80c51rd2 7. dual data pointer register the additional data pointer can be used to speed up code execution and reduce code size. the dual dptr structure is a wa y by which the chip will specify th e address of an external data memory location. there are two 16-bit dptr registers that address the external memory, and a single bit called dps = auxr1.0 (see table 7-1 ) that allows the program code to switch between them (refer to figure 7-1). figure 7-1. use of dual pointer table 7-1. auxr1 register auxr1- auxiliary register 1(0a2h) reset value: xxxx xxxx0b not bit addressable note: 1. bit 2 stuck at 0; this allows to us e inc auxr1 to toggle dps without changing gf3. external data memory auxr1(a2h) dps dph(83h) dpl(82h) 0 7 dptr0 dptr1 76543210 ----gf30-dps bit number bit mnemonic description 7- reserved the value read from this bit is i ndeterminate. do not set this bit. 6- reserved the value read from this bit is i ndeterminate. do not set this bit. 5-reserved 4- reserved the value read from this bit is i ndeterminate. do not set this bit. 3 gf3 this bit is a general purpose user flag. 2 0 always cleared (1) . 1- reserved the value read from this bit is i ndeterminate. do not set this bit. 0dps data pointer selection cleared to select dptr0. set to select dptr1.
13 4113d?8051?01/09 at80c51rd2 7.1 assembly language ; block move using dual data pointers ; modifies dptr0, dptr1, a and psw ; note: dps exits opposite of entry state ; unless an extra inc auxr1 is added ; 00a2 auxr1 equ 0a2h ; 0000 909000mov dptr,#source ; address of source 0003 05a2 inc auxr1 ; switch data pointers 0005 90a000 mov dptr,#dest ; address of dest 0008 loop: 0008 05a2 inc auxr1 ; switch data pointers 000a e0 movx a,@dptr ; get a byte from source 000b a3 inc dptr ; increment source address 000c 05a2 inc auxr1 ; switch data pointers 000e f0 movx @dptr,a ; write the byte to dest 000f a3 inc dptr ; increment dest address 0010 70f6jnz loop ; check for 0 terminator 0012 05a2 inc auxr1 ; (optional) restore dps inc is a short (2 bytes) and fast (12 clocks) way to manipulate the dps bit in the auxr1 sfr. however, note that the inc instruction does not directly force the dps bit to a particular state, but simply toggles it. in simple routines, such as the block move example, only the fact that dps is toggled in the proper sequence matters, not its actual value. in other words, the block move routine works the same whether dps is '0' or '1' on entry. observe that without the last instruc- tion (inc auxr1), the routine will exit with dps in the opposite state.
14 4113d?8051?01/09 at80c51rd2 8. expanded ram (xram) the at80c51rd2 devices provide additional bytes of random access memory (ram) space for increased data parameter handling and high level language usage. the devices have expanded ram in external dat a space; maximum size and location are described in table 8-1. table 8-1. expanded ram the at80c51rd2 has internal data memory t hat is mapped into four separate segments. the four segments are: 1. the lower 128 bytes of ram (addresses 00h to 7fh) are directly and indirectly addressable. 2. the upper 128 bytes of ram (addresses 80h to ffh) are indirectly addressable only. 3. the special function registers (sfrs) (add resses 80h to ffh) are directly address- able only. 4. the expanded ram bytes are indirectly accessed by movx instructions, and with the extram bit cleared in the auxr register (see table 8-1). the lower 128 bytes can be accessed by either direct or indirect addressing. the upper 128 bytes can be accessed by indirect addressing only. the upper 128 bytes occupy the same address space as the sfr. that means they have the same address, but are physically sepa- rate from sfr space. figure 8-1. internal and external data memory address when an instruction accesses an internal location above address 7fh, the cpu knows whether the access is to the upper 128 bytes of data ram or to sfr space by the addressing mode used in the instruction. ? instructions that use direct addressing access sfr space. for example: mov 0a0h, # data, accesses the sfr at locati on 0a0h (which is p2). xram size address start end t83c51rb2/rc2 t80c51rd2 1024 00h 3ffh xram upper 128 bytes internal ram lower 128 bytes internal ram special function register 80h 80h 00 0ffh or 3ffh 0ffh 00 0ffh external data memory 0000 00ffh up to 03ffh 0ffffh indirect accesses direct accesses direct or indirect accesses 7fh
15 4113d?8051?01/09 at80c51rd2 ? instructions that use indirect addressing access the upper 128 bytes of data ram. for example: mov @r0, # data where r0 contains 0a0h, accesses the data byte at address 0a0h, rather than p2 (whose address is 0a0h). ? the xram bytes can be accessed by indirect addressing, with extram bit cleared and movx instructions. this part of memory whic h is physically located on-chip, logically occupies the first bytes of external data memory. the bits xrs0 and xrs1 are used to hide a part of the available xram as explained in table 8-1. this can be useful if external peripherals are mapped at addresses already used by the internal xram. ? with extram = 0, the xram is indirectly addressed, using the movx instruction in combination with any of the registers r0, r1 of the selected bank or dptr. an access to xram will not affect ports p0, p2, p3.6 (wr) and p3.7 (rd). for example, with extram = 0, movx @r0, # data where r0 contains 0a0h, accesses the xram at address 0a0h rather than external memory. an access to external data memory locations higher than the accessible size of the xram w ill be performed with the movx dptr instructions in the same way as in the standard 80c51, with p0 and p2 as data/address busses, and p3.6 and p3.7 as write and read timing signals. accesses to xram above 0ffh can only be done by the use of dptr. ?with extram = 1 , movx @ri and movx @dptr will be si milar to the standard 80c51. movx @ ri will provide an eight-bi t address multiplexed with da ta on port 0 and any output port pins can be used to output higher order address bits. this is to provide the external paging capability. movx @dptr will generate a si xteen-bit address. po rt2 outputs the high- order eight address bits (the contents of dph) while port0 multiplexes the low-order eight address bits (dpl) with data . movx @ ri and movx @dptr will generate either read or write signals on p3.6 (wr ) and p3.7 (rd ). the stack pointer (sp) may be located anywhere in the 256 bytes ram (lower and upper ram) internal data memory . the stack may not be located in the xram. the m0 bit allows to stretch the xram timings; if m0 is set, the read and write pulses are extended from 6 to 30 clock periods. this is useful to access external slow peripherals. table 8-2. auxr register auxr - auxiliary register (8eh) 76543210 - - m0 - xrs1 xrs0 extram ao bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit 6- reserved the value read from this bit is indeterminate. do not set this bit 5m0 pulse length cleared to stretch movx control: the rd and the wr pulse length is 6 clock periods (default). set to stretch movx control: the rd and the wr pulse length is 30 clock periods. 4- reserved the value read from this bit is indeterminate. do not set this bit
16 4113d?8051?01/09 at80c51rd2 reset value = xx0x 00?hsb.xram?0b (see table 8-1 ) not bit addressable 3xrs1 xram size xrs1 xrs0 xram size 0 0 256 bytes (default) 0 1 512 bytes 1 0 768 bytes 1 1 1024 bytes 2xrs0 1extram extram bit cleared to access internal xram using movx @ ri/ @ dptr. set to access external memory. programmed by hardware after power-up regarding hardware security byte (hsb), default setting, xram selected. 0ao ale output bit cleared, ale is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if x2 mode is used) (default). set, ale is active only if a movx or movc instruction is used. bit number bit mnemonic description
17 4113d?8051?01/09 at80c51rd2 9. timer 2 the timer 2 in the at80c51rd2 is the standard c52 timer 2. it is a 16-bit timer/counter: t he count is maintained by two eight-bit timer registers, th2 and tl2 are cascaded. it is controlled by t2con (tabl e 9-1) and t2mod (table 9-2) registers. timer 2 operation is similar to timer 0 and timer 1. c/t2 selects f osc /12 (timer operation) or external pin t2 (counter operation) as the timer clock input. setting tr2 allows tl2 to be incremented by the selected input. timer 2 has 3 operating modes: capture, auto-reload and baud rate generator. these modes are selected by the combination of rclk, tclk and cp/rl2 (t2con). refer to the atmel 8-bit microcontroller hardware description for capture and baud rate gen- erator modes. timer 2 includes the following enhancements: ? auto-reload mode with up or down counter ? programmable clock-output 9.1 auto-reload mode the auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. if dcen bit in t2mod is cleared, timer 2 behaves as in 80c52 (refer to the atmel 8-bit microcontroller hardware description). if dc en bit is set, timer 2 acts as an up/down timer/counter as shown in figure 9-1. in this m ode the t2ex pin controls the direction of count. when t2ex is high, timer 2 counts up. timer overflow occurs at ffffh which sets the tf2 flag and generates an interrupt request. the overflow also causes the 16-bit value in rcap2h and rcap2l registers to be loaded into the timer registers th2 and tl2. when t2ex is low, timer 2 counts down. timer underflow occurs when the count in the timer registers th2 and tl2 equals the value stored in rcap2h and rcap2l registers. the under- flow sets tf2 flag and reloads ffffh into the timer registers. the exf2 bit toggles when timer 2 overflows or underflows according to the direction of the count. exf2 does not generate any interrupt. this bit can be used to provide 17-bit resolution.
18 4113d?8051?01/09 at80c51rd2 figure 9-1. auto-reload mode up/down counter (dcen = 1) 9.2 programmable clock-output in the clock-out mode, timer 2 operates as a 50% duty-cycle, programmable clock generator (see figure 9-2). the input clock increments tl2 at frequency f clk periph /2. the timer repeat- edly counts to overflow from a loaded value. at overflow, the contents of rcap2h and rcap2l registers are loaded into th2 and tl2. in this mode, timer 2 overflows do not generate inter- rupts. the formula gives the clock-out frequency as a function of the system oscillator frequency and the value in the rcap2h and rcap2l registers: for a 16 mhz system clock, timer 2 has a programmable frequency range of 61 hz (f clk periph /2 16) to 4 mhz (f clk periph /4). the generated clock signal is brought out to t2 pin (p1.0). timer 2 is programmed for the clock-out mode as follows: ? set t2oe bit in t2mod register. ? clear c/t2 bit in t2con register. ? determine the 16-bit reload value from the formula and enter it in rcap2h/rcap2l registers. ? enter a 16-bit initial value in timer registers th2/tl2. it can be the same as the reload value or a different one depending on the application. ? to start the timer, set tr2 run control bit in t2con register. (down counting reload value) c/t 2 tf2 tr2 t2 exf2 th2 (8-bit) tl2 (8-bit) rcap2h (8-bit) rcap2l (8-bit) ffh (8-bit) ffh (8-bit) toggle (up counting reload value) timer 2 interrupt f clk periph 0 1 t2con t2con t2con t2con t2ex: if dcen = 1, 1 = up if dcen = 1, 0 = down if dcen = 0, up counting :6 clock outfrequency ? f clkperiph 4 65536 rcap 2 h ? rcap 2 l ? () ---------------------------------------------------------------------------------------- - =
19 4113d?8051?01/09 at80c51rd2 it is possible to use timer 2 as a baud rate ge nerator and a clock generator simultaneously. for this configuration, the baud rates and clock frequencies are not independent since both func- tions use the values in the rcap2h and rcap2l registers. figure 9-2. clock-out mode c/t2 = 07 table 9-1. t2con register t2con - timer 2 control register (c8h) 76543210 tf2 exf2 rclk tclk exen2 tr2 c/t2# cp/rl2# :6 exf2 tr2 oveflow t2ex th2 (8-bit) tl2 (8-bit) timer 2 rcap2h (8-bit) rcap2l (8-bit) t2oe t2 f clk periph t2con t2con t2con t2mod interrupt qd toggle exen2
20 4113d?8051?01/09 at80c51rd2 reset value = 0000 0000b bit addressable bit number bit mnemonic description 7tf2 timer 2 overflow flag must be cleared by software. set by hardware on timer 2 overfl ow, if rclk = 0 and tclk = 0. 6exf2 timer 2 external flag set when a capture or a reload is caused by a negative transition on t2ex pin if exen2 = 1. when set, causes the cpu to vector to time r 2 interrupt routine when timer 2 interrupt is enabled. must be cleared by software. exf2 doesn?t cause an interrupt in up/down counter mode (dcen = 1) 5 rclk receive clock bit cleared to use timer 1 overflow as rece ive clock for serial port in mode 1 or 3. set to use timer 2 overflow as receive clock for serial port in mode 1 or 3. 4tclk transmit clock bit cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. set to use timer 2 overflow as transmi t clock for serial port in mode 1 or 3. 3 exen2 timer 2 external enable bit cleared to ignore events on t2ex pin for timer 2 operation. set to cause a capture or reload when a negativ e transition on t2ex pin is detected, if timer 2 is not used to clock the serial port. 2tr2 timer 2 run control bit cleared to turn off timer 2. set to turn on timer 2. 1c/t2# timer/counter 2 select bit cleared for timer operation (input from internal clock system: f clk periph ). set for counter operation (input from t2 inpu t pin, falling edge trigger). must be 0 for clock out mode. 0cp/rl2# timer 2 capture/reload bit if rclk = 1 or tclk = 1, cp/rl2# is i gnored and timer is forced to auto-reload on timer 2 overflow. cleared to auto-reload on timer 2 overfl ows or negative transitions on t2ex pin if exen2 = 1. set to capture on negative transitions on t2ex pin if exen2 = 1.
21 4113d?8051?01/09 at80c51rd2 table 9-2. t2mod register t2mod - timer 2 mode control register (c9h) reset value = xxxx xx00b not bit addressable 76543210 ------t2oedcen bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3- reserved the value read from this bit is indeterminate. do not set this bit. 2- reserved the value read from this bit is indeterminate. do not set this bit. 1t2oe timer 2 output enable bit cleared to program p1.0/t2 as clock input or i/o port. set to program p1.0/t2 as clock output. 0 dcen down counter enable bit cleared to disable timer 2 as up/down counter. set to enable timer 2 as up/down counter.
22 4113d?8051?01/09 at80c51rd2 10. programmable counter array (pca) the pca provides more timing capabilities wit h less cpu intervent ion than the standard timer/counters. its advantages include reduced software overhead and improved accuracy. the pca consists of a dedicated timer/counter whic h serves as the time base for an array of five compare/capture modules. its clock input can be programmed to count any one of the following signals: ? peripheral clock frequency (f clk periph ) 6 ? peripheral clock frequency (f clk periph ) 2 ? timer 0 overflow ? external input on eci (p1.2) each compare/capture modules can be programmed in any one of the following modes: ? rising and/or falling edge capture ? software timer ? high-speed output ? pulse width modulator module 4 can also be programmed as a watchd og timer (see section "pca watchdog timer", page 33). when the compare/capture modules are programmed in the capture mode, software timer, or high-speed output mode, an interrupt can be generated when the module executes its function. all five modules plus the pca timer overflow share one interrupt vector. the pca timer/counter and compare/capture modules share port 1 for external i/o. these pins are listed below. if the port is not used for the pca, it c an still be used for standard i/o. the pca timer is a common time base for all fi ve modules (see figure 10-1). the timer count source is determined from the cps1 and cps0 bits in the cmod register (table 10-1) and can be programmed to run at: ? 1/6 the peripheral clock frequency (f clk periph ) ? 1/2 the peripheral clock frequency (f clk periph ) ? the timer 0 overflow ? the input on the eci pin (p1.2) pca component external i/o pin 16-bit counter p1.2/eci 16-bit module 0 p1.3/cex0 16-bit module 1 p1.4/cex1 16-bit module 2 p1.5/cex2 16-bit module 3 p1.6/cex3
23 4113d?8051?01/09 at80c51rd2 figure 10-1. pca timer/counter cidl cps1 cps0 ecf it ch cl 16-bit up/down counter to pca modules f clk periph /6 f clk periph /2 t0 ovf p1.2 idle cmod 0xd9 wdte cf cr ccon 0xd8 ccf4 ccf3 ccf2 ccf1 ccf0 overflow
24 4113d?8051?01/09 at80c51rd2 table 10-1. cmod register cmod - pca counter mode register (d9h) reset value = 00xx x000b not bit addressable the cmod register includes three additional bi ts associated with the pca (see figure 10-4 and table 10-1). ? the cidl bit which allows the pca to stop during idle mode. ? the wdte bit which enables or disabl es the watchdog function on module 4. ? the ecf bit which when set causes an interrupt and the pca overflow flag cf (in the ccon sfr) to be set when the pca timer overflows. the ccon register contains the run control bit for the pca and the flags for the pca timer (cf) and each module (see table 10-2). ? bit cr (ccon.6) must be set by software to run the pca. the pca is shut off by clearing this bit. ? bit cf: the cf bit (ccon.7) is set when th e pca counter overflows and an interrupt will be generated if the ecf bit in the cmod register is set. the cf bit can only be cleared by software. 76543210 cidl wdte - - - cps1 cps0 ecf bit number bit mnemonic description 7cidl counter idle control cleared to program the pca counter to continue functioning during idle mode. set to program pca to be gated off during idle. 6wdte watchdog timer enable cleared to disable watchdog timer function on pca module 4. set to enable watchdog timer function on pca module 4. 5- reserved the value read from this bit is i ndeterminate. do not set this bit. 4- reserved the value read from this bit is i ndeterminate. do not set this bit. 3- reserved the value read from this bit is i ndeterminate. do not set this bit. 2cps1 pca count pulse select cps1cps0 selected pca input 0 0 internal clock f clk periph/6 0 1 internal clock f clk periph/2 1 0 timer 0 overflow 1 1 external clock at eci/p1.2 pin (max rate = f clk periph/4 ) 1cps0 0ecf pca enable counter overflow interrupt cleared to disable cf bit in ccon to inhibit an interrupt. set to enable cf bit in ccon to generate an interrupt.
25 4113d?8051?01/09 at80c51rd2 ? bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. these flags can only be cleared by software. table 10-2. ccon register ccon - pca counter control register (d8h) reset value = 000x 0000b not bit addressable the watchdog timer function is implemented in module 4 (see figure 10-4). the pca interrupt system is shown in figure 10-2. 76543210 cf cr - ccf4 ccf3 ccf2 ccf1 ccf0 bit number bit mnemonic description 7cf pca counter overflow flag set by hardware when the counter rolls over. cf flags an interrupt if bit ecf in cmod is set. cf may be set by either hardware or software but can only be cleared by software. 6cr pca counter run control bit must be cleared by software to turn the pca counter off. set by software to turn the pca counter on. 5- reserved the value read from this bit is i ndeterminate. do not set this bit. 4ccf4 pca module 4 interrupt flag must be cleared by software. set by hardware when a match or capture occurs. 3ccf3 pca module 3 interrupt flag must be cleared by software. set by hardware when a match or capture occurs. 2ccf2 pca module 2 interrupt flag must be cleared by software. set by hardware when a match or capture occurs. 1ccf1 pca module 1 interrupt flag must be cleared by software. set by hardware when a match or capture occurs. 0ccf0 pca module 0 interrupt flag must be cleared by software. set by hardware when a match or capture occurs.
26 4113d?8051?01/09 at80c51rd2 figure 10-2. pca interrupt system pca modules: each one of the five compare/capture modules has six possible functions. it can perform: ? 16-bit capture, positive-edge triggered ? 16-bit capture, negative-edge triggered ? 16-bit capture, both positive and negative-edge triggered ? 16-bit software timer ? 16-bit high-speed output ? 8-bit pulse width modulator in addition, module 4 can be used as a watchdog timer. each module in the pca has a s pecial function register associated with it. these registers are: ccapm0 for module 0, ccapm1 for module 1, etc. (see table 10-3). the registers contain the bits that control the mode th at each module will operate in. ? the eccf bit (ccapmn.0 where n = 0, 1, 2, 3, or 4 depending on the module) enables the ccf flag in the ccon sfr to generate an interrupt when a match or compare occurs in the associated module. ? pwm (ccapmn.1) enables the pulse width modulation mode. ? the tog bit (ccapmn.2) when set causes the cex output associated with the module to toggle when there is a match between the pca counter and the module's capture/compare register. ? the match bit mat (ccapmn.3) when set will ca use the ccfn bit in the ccon register to be set when there is a match between the pca counter and the module's capture/compare register. ? the next two bits capn (ccapmn.4) and capp (ccapmn.5) determ ine the edge that a capture input will be active on. the capn bi t enables the negative edge, and the capp bit enables the positive edge. if both bits are se t both edges will be enab led and a capture will occur for either transition. ? the last bit in the register ecom (ccapmn.6) when set enables the comparator function. cf cr ccon 0xd8 ccf4 ccf3 ccf2 ccf1 ccf0 module 4 module 3 module 2 module 1 module 0 ecf pca timer/counter eccfn ccapmn.0 cmod.0 ie.6 ie.7 to interrupt priority decoder ec ea
27 4113d?8051?01/09 at80c51rd2 table 10-3 shows the ccapmn settings for the various pca functions. table 10-3. ccapmn registers (n = 0-4) ccapm0 - pca module 0 compare/capture control register (0dah) ccapm1 - pca module 1 compare/capture control register (0dbh) ccapm2 - pca module 2 compare/capture control register (0dch) ccapm3 - pca module 3 compare/capture control register (0ddh) ccapm4 - pca module 4 compare/capture control register (0deh) reset value = x000 0000b not bit addressable 76543210 - ecomn cappn capnn matn togn pwmn eccfn bit number bit mnemonic description 7- reserved the value read from this bit is i ndeterminate. do not set this bit. 6ecomn enable comparator cleared to disable the comparator function. set to enable the comparator function. 5 cappn capture positive cleared to disable positive edge capture. set to enable positive edge capture. 4 capnn capture negative cleared to disable negative edge capture. set to enable negative edge capture. 3matn match when matn = 1, a match of the pca counter with this module's compare/capture register causes the ccfn bit in ccon to be set, flagging an interrupt. 2togn toggle when togn = 1, a match of the pca counter with this module's compare/capture register causes the cexn pin to toggle. 1pwmn pulse width modulation mode cleared to disable the cexn pin to be used as a pulse width modulated output. set to enable the cexn pin to be used as a pulse width modulated output. 0ccf0 enable ccf interrupt cleared to disable compare/capture flag ccfn in the ccon register to generate an interrupt. set to enable compare/capture flag ccfn in the ccon register to generate an interrupt.
28 4113d?8051?01/09 at80c51rd2 table 10-4. pca module modes (ccapmn registers) there are two additional registers associated with each of the pca modules. they are ccapnh and ccapnl and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. when a module is used in the pwm mode these registers are used to control the duty cycle of the output (see table 10-5 and table 10-6). table 10-5. ccapnh registers (n = 0-4) ccap0h - pca module 0 compare/capture control register high (0fah) ccap1h - pca module 1 compare/capture control register high (0fbh) ccap2h - pca module 2 compare/capture control register high (0fch) ccap3h - pca module 3 compare/capture control register high (0fdh) ccap4h - pca module 4 compare/capture control register high (0feh) reset value = 0000 0000b not bit addressable ecomn cappn capnn matn togn pwmm eccfn module function 0000000 no operation x10000x 16-bit capture by a positive-edge trigger on cexn x01000x 16-bit capture by a negative trigger on cexn x11000x16-bit capture by a transition on cexn 100100x 16-bit software timer/compare mode. 100110x 16-bit high-s peed output 1000010 8-bit pwm 1001x0x watc hdog timer (module 4 only) 76543210 -------- bit number bit mnemonic description 7-0 - pca module n compare/capture control ccapnh value
29 4113d?8051?01/09 at80c51rd2 table 10-6. ccapnl registers (n = 0-4) ccap0l - pca module 0 compare/capture control register low (0eah) ccap1l - pca module 1 compare/capture control register low (0ebh) ccap2l - pca module 2 compare/capture control register low (0ech) ccap3l - pca module 3 compare/capture control register low (0edh) ccap4l - pca module 4 compare/capture control register low (0eeh) reset value = 0000 0000b not bit addressable table 10-7. ch register ch - pca counter register high (0f9h) reset value = 0000 0000b not bit addressable table 10-8. cl register cl - pca counter register low (0e9h) reset value = 0000 0000b not bit addressable 76543210 -------- bit number bit mnemonic description 7-0 - pca module n compare/capture control ccapnl value 76543210 -------- bit number bit mnemonic description 7-0 - pca counter ch value 76543210 -------- bit number bit mnemonic description 7-0 - pca counter cl value
30 4113d?8051?01/09 at80c51rd2 10.1 pca capture mode to use one of the pca modules in the capture mode either one or both of the ccapm bits capn and capp for that module mu st be set. the external cex in put for the module (on port 1) is sampled for a transition. when a valid transi tion occurs the pca hardware loads the value of the pca counter registers (ch and cl) into the module's capture registers (ccapnl and cca- pnh). if the ccfn bit for the module in the ccon sfr and the eccfn bit in the ccapmn sfr are set then an inte rrupt will be generated (see figure 10-3). figure 10-3. pca capture mode 10.2 16-bit software timer/ compare mode the pca modules can be used as software time rs by setting both the ecom and mat bits in the modules ccapmn register. the pca timer wil l be compared to the module's capture regis- ters and when a match occurs an interrupt will occur if the ccfn (ccon sfr) and the eccfn (ccapmn sfr) bits for the module are both set (see figure 10-4). cf cr ccon 0xd8 ch c l cc ap nh c ca pn l ccf4 ccf3 ccf2 ccf1 ccf0 pca it pca coun te r/timer ecomn ccapmn, n= 0 to 4 0xda to 0xde capnn matn togn pwmn eccfn cappn cex.n capture
31 4113d?8051?01/09 at80c51rd2 figure 10-4. pca compare mode and pca watchdog timer before enabling ecom bit, ccapnl and ccapnh should be set with a non zero value, other- wise an unwanted match coul d happen. writing to cc apnh will set the ecom bit. once ecom set, writing ccapnl will clear ecom so that an unwanted match doesn?t occur while modifying the compare va lue. writing to ccapnh will set ecom. for this reason, user software should write ccapnl first, and then cca pnh. of course, the ecom bit can still be controlled by accessing to ccapmn register. 10.3 high-speed output mode in this mode, the cex output (on port 1) associated with the pc a module will toggle each time a match occurs between the pca counter and the module's capture registers. to activate this mode the tog, mat, and ecom bits in the module's ccapmn sfr must be set (see figure 10-5). a prior write must be done to ccapnl and ccapnh before writing the ecomn bit. ch c l cc ap nh c ca pn l ecomn cca pmn, n = 0 to 4 0xda to 0xde capnn matn togn pwmn eccfn ca ppn 16 bit comparator ma tch cc on 0xd8 pca i t en ab le pca cou nter/ timer reset * cidl cps1 cps0 ecf cm od 0xd9 wd te reset write to ccapnl wr ite t o ccapnh cf c c f 2 cc f 1 c c f0 cr ccf3 ccf4 10
32 4113d?8051?01/09 at80c51rd2 figure 10-5. pca high-speed output mode before enabling ecom bit, ccapnl and ccapnh should be set with a non zero value, other- wise an unwanted match could occur. once ecom is set, writing ccapnl will clear ecom so that an unwant ed match doesn?t occur while modifying the compare va lue. writing to ccapnh will set ecom. for this reason, user software should write ccapnl first, and then cca pnh. of course, the ecom bit can still be controlled by accessing the ccapmn register. 10.4 pulse width modulator mode all of the pca modules can be used as pwm outputs. figure 10-6 shows the pwm function. the frequency of the output de pends on the source for the pc a timer. all of the modules will have the same frequency of output because they all share the pca timer. the duty cycle of each module is independently variable using the module's capture register ccapln. when the value of the pca cl sfr is less than the value in the module's ccapln sfr the output will be low, when it is equal to or greater than the output will be high. when cl overflows from ff to 00, ccapln is reloaded with the value in ccaphn. this allows updating the pwm without glitches. the pwm and ecom bits in the module's ccap mn register must be set to enable the pwm mode. ch cl ccapnh ccapnl ecomn cca pmn, n = 0 to 4 0xda to 0xde capnn matn togn p wmn eccfn cappn 16 bit comparator ma tch cf cr ccon 0xd8 ccf4 ccf3 ccf2 ccf1 ccf0 pca it enable cexn pca counter/timer write to ccapnh reset write to ccapnl 1 0
33 4113d?8051?01/09 at80c51rd2 figure 10-6. pca pwm mode 10.5 pca watchdog timer an on-board watchd og timer is available with the pca to improve the reliability of the system without increasing chip count. watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge . module 4 is the only pca module that can be programmed as a watchdog. however, this module can still be used for other modes if the watchdog is not needed. figure 10-4 shows a diagram of how the watchdog works. the user pre-loads a 16-bit value in the compare registers. just like the other compare modes, this 16-bit value is compared to the pca ti mer value. if a match is allowed to occur, an internal reset will be generated. this will no t cause the rst pin to be driven high. in order to hold off the reset, the user has three options: 1. periodically change the compare valu e so it will never match the pca timer. 2. periodically change the pca timer value so it will never match the compare values. 3. disable the watchdog by clearing the wdte bit before a match occurs and then re- enable it. the first two options are more reliable because the watchdog timer is never disabled as in option #3. if the program counte r ever goes astray, a match will eventually occu r and cause an internal reset. the second option is also not reco mmended if other pca modules are being used. remember, the pca timer is the time base fo r all modules; changing the time base for other modules would not be a good idea. thus, in most a pplications the first solution is the best option. this watchdog timer won?t generate a reset out on the reset pin. cl ccapnh ccapnl ecomn ccapmn, n= 0 to 4 0xda to 0xde capnn matn togn pwmn eccfn cappn 8-bit comparator cexn ?0? ?1? enable pca counter/timer overflow
34 4113d?8051?01/09 at80c51rd2 11. serial i/o port the serial i/o port in the at80c51rd2 is compatible with the serial i/o port in the 80c52. it provides both synchronous and asynchronous communication modes. it operates as a univer- sal asynchronous receiver and transmitter (uart) in three full-duplex modes (modes 1, 2 and 3). asynchronous transmission and reception can occur simultaneously and at different baud rates serial i/o port includes the following enhancements: ? framing error detection ? automatic address recognition 11.1 framing error detection framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). to enable the framing bit error detection feature, set smod0 bit in pcon register (see figure 11- 1). figure 11-1. framing error block diagram when this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. an invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two cpus. if a valid stop bit is not found, the framing error bit (fe) in scon register (see table 11-4 ) bit is set. software may examine fe bit after each reception to check for data errors. once set, only soft- ware or a reset can clear fe bit. subsequently, re ceived frames with valid stop bits cannot clear fe bit. when fe feature is enabled, ri rises on stop bit instead of the last data bit (see figure 11-2 and figure 11-3 ). figure 11-2. uart timings in mode 1 ri ti rb8 tb8 ren sm 2 sm 1 sm 0/fe idl pd gf0 gf1 po f - sm od0 sm od1 t o ua rt fra min g e rr o r co nt ro l sm 0 to ua rt m o de con tro l (sm od 0 = 0 ) se t fe bit if stop bit is 0 (fram ing erro r) (sm od 0 = 1) scon (98h) pcon (87 h) 1 data byte ri smod0=x sto p bit sta rt bit rxd d7 d6 d5 d4 d3 d2 d1 d0 fe smod0=1
35 4113d?8051?01/09 at80c51rd2 figure 11-3. uart timings in modes 2 and 3 11.2 automatic ad dress recognition the automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (sm2 bit in scon register is set). implemented in hardware, automatic address recognition enhances the multiprocessor commu- nication feature by allowing the serial port to examine the address of each incoming command frame. only when the serial port recognizes its own address, the receiver sets ri bit in scon register to generate an interrupt. this ensures that the cpu is not interrupted by command frames addressed to other devices. if desired, you may enable the automatic address recognition feature in mode 1. in this configu- ration, the stop bit takes the place of the ninth data bit. bit ri is set only when the received command frame address matches the device?s address and is terminated by a valid stop bit. to support automatic address recognition, a device is identified by a given address and a broad- cast address. note: the multiprocessor communication and auto matic address recogniti on features cannot be enabled in mode 0 (i.e. setting sm2 bit in scon register in mode 0 has no effect). 11.2.1 given address each device has an individual address that is specified in saddr register; the saden register is a mask byte that contains don?t care bits (defined by zeros) to form the device?s given address. the don?t care bits provi de the flexibility to address one or more slaves at a time. the following example illustrates ho w a given address is formed. to address a device by its individual address, the saden mask byte must be 1111 1111b . for example: saddr0101 0110b saden 1111 1100b given0101 01xxb the following is an example of how to use gi ven addresses to addr ess different slaves: slave a:saddr1111 0001b saden 1111 1010b given1111 0x0xb slave b:saddr1111 0011b saden 1111 1001b ri smod0 = 0 data byte ninth bit stop bit .start bit rxd d8 d7 d6 d5 d4 d3 d2 d1 d0 ri smod0 = 1 fe smod0 = 1
36 4113d?8051?01/09 at80c51rd2 given1111 0xx1b slave c:saddr1111 0010b saden 1111 1101b given1111 00x1b the saden byte is selected so that each slave may be addressed separately. for slave a, bit 0 (the lsb) is a don?t-care bit; for slaves b and c, bit 0 is a 1. to communicate with slave a only, the master must send an address where bit 0 is clear (e.g. 1111 0000b ). for slave a, bit 1 is a 1; for slaves b and c, bit 1 is a don?t care bit. to communicate with slaves b and c, but not slave a, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b ). to communicate with slaves a, b and c, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b ). 11.2.2 broadcast address a broadcast address is formed from the logical or of the saddr and saden registers with zeros defined as don?t-care bits, e.g.: saddr0101 0110b saden1111 1100b broadcast = saddr or saden1111 111xb the use of don?t-care bits provid es flexibility in defining the br oadcast address, however in most applications, a broadcast address is ffh. t he following is an example of using broadcast addresses: slave a:saddr1111 0001b saden 1111 1010b broadcast1111 1x11b, slave b:saddr1111 0011b saden 1111 1001b broadcast1111 1x11b, slave c:saddr = 1111 0010b saden 1111 1101b broadcast1111 1111b for slaves a and b, bit 2 is a don?t care bit; for slave c, bit 2 is set. to communicate with all of the slaves, the master must send an address ffh. to communicate with slaves a and b, but not slave c, the master can send and address fbh.
37 4113d?8051?01/09 at80c51rd2 11.2.3 reset addresses on reset, the saddr and saden registers are initialized to 00h, i.e. the given and broadcast addresses are xxxx xxxxb (all don?t-care bits). this ensures th at the serial port will reply to any address, and so, that it is backwards compatible with the 80c51 microcontrollers that do not support automatic address recognition. table 11-1. saden register saden - slave address mask register (b9h) reset value = 0000 0000b not bit addressable table 11-2. saddr register saddr - slave address register (a9h) reset value = 0000 0000b not bit addressable 11.3 baud rate selection fo r uart for mode 1 and 3 the baud rate generator for transmit and receive clocks can be selected separately via the t2con and bdrcon registers. figure 11-4. baud rate selection 76543210 76543210 rclk / 16 rb c k int_brg 0 1 timer1 0 1 0 1 timer2 int_b rg timer1 ti me r2 ti me r_ br g_ rx rx clock / 16 0 1 timer_brg_tx tx clock tb c k tclk
38 4113d?8051?01/09 at80c51rd2 table 11-3. baud rate selection table uart 11.3.1 internal baud rate generator (brg) when the internal baud rate generator is used, the baud rates are determined by the brg overflow depending on the brl reload value, the value of spd bit (speed mode) in bdrcon register and the value of the smod1 bit in pcon register. figure 11-5. internal baud rate ? the baud rate for uart is token by formula: tclk (t2con) rclk (t2con) tbck (bdrcon) rbck (bdrcon) clock source uart tx clock source uart rx 0000timer 1timer 1 1000timer 2timer 1 0100timer 1timer 2 1100timer 2timer 2 x010int_brgtimer 1 x110int_brgtimer 2 0 x 0 1 timer 1 int_brg 1 x 0 1 timer 2 int_brg x x 1 1 int_brg int_brg peripheral clock brg 0 1 /6 brl /2 0 1 int_brg brr auto reload counter overflow spd baudrate 2 smod f clkperiph 226 1 spd ? ?? 16 256 brl () ? [] --------------------------------------------------------------------------------------------------------- - = brl () 256 2 smod 1 f clkperiph 226 1 spd ? () 16 baudrate ---------------------------------------------------------------------------------------- - ? =
39 4113d?8051?01/09 at80c51rd2 table 11-4. scon register scon - serial control register (98h) reset value = 0000 0000b bit addressable 76543210 fe/sm0 sm1 sm2 ren tb8 rb8 ti ri bit number bit mnemonic description 7fe framing error bit (smod0 = 1 ) clear to reset the error state, not cleared by a valid stop bit. set by hardware when an invalid stop bit is detected. smod0 must be set to enable access to the fe bit sm0 serial port mode bit 0 refer to sm1 for serial port mode selection. smod0 must be cleared to enable access to the sm0 bit 6sm1 serial port mode bit 1 sm1 mode description baud rat e 0 0shift registerf cpu periph/6 1 18-bit uartvariable 0 29-bit uartf cpu periph /32 or /16 1 39-bit uartvariable 5sm2 serial port mode 2 bit/multiprocessor communication enable bit clear to disable multiprocessor communication feature. set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. this bit should be cleared in mode 0. 4ren reception enable bit clear to disable serial reception. set to enable serial reception. 3tb8 transmitter bit 8/ninth bit to transmit in modes 2 and 3 o transmit a logic 0 in the 9th bit. set to transmit a logic 1 in the 9th bit. 2rb8 receiver bit 8/ninth bit received in modes 2 and 3 cleared by hardware if 9th bit received is a logic 0. set by hardware if 9th bit received is a logic 1. in mode 1, if sm2=0, rb8 is the received stop bit. in mode 0 rb8 is not used. 1ti transmit interrupt flag clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. 0ri receive interrupt flag clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0, see figure 11-2. and figure 11-3. in the other modes.
40 4113d?8051?01/09 at80c51rd2 table 11-5. example of computed value when x2 = 1, smod1 = 1, spd = 1 table 11-6. example of computed value when x2 = 0, smod1 = 0, spd = 0 the baud rate generator can be used for mode 1 or 3 (see figure 11-4.), but also for mode 0 for uart, thanks to the bit src located in bdrcon register (table 11-13.) 11.4 uart registers table 11-7. saden register saden - slave address mask register for uart (b9h) reset value = 0000 0000b table 11-8. saddr register saddr - slave address register for uart (a9h) reset value = 0000 0000b baud rates f osc =16.384 mhz f osc =24 mhz brl error (%) brl error (%) 115200 247 1.23 243 0.16 57600 238 1.23 230 0.16 38400 229 1.23 217 0.16 28800 220 1.23 204 0.16 19200 203 0.63 178 0.16 9600 149 0.31 100 0.16 4800 43 1.23 - - baud rates f osc =16.384 mhz f osc =24 mhz brl error (%) brl error (%) 4800 247 1.23 243 0.16 2400 238 1.23 230 0.16 1200 220 1.23 202 3.55 600 185 0.16 152 0.16 76543210 76543210
41 4113d?8051?01/09 at80c51rd2 table 11-9. sbuf register sbuf - serial buffer register for uart (99h) reset value = xxxx xxxxb table 11-10. brl register brl - baud rate reload register for the internal baud rate generator, uart (9ah) reset value = 0000 0000b 76543210 76543210
42 4113d?8051?01/09 at80c51rd2 table 11-11. t2con register t2con - timer 2 control register (c8h) reset value = 0000 0000b bit addressable 76543210 tf2 exf2 rclk tclk exen2 tr2 c/t2# cp/rl2# bit number bit mnemonic description 7tf2 timer 2 overflow flag must be cleared by software. set by hardware on timer 2 overflow, if rclk=0 and tclk=0. 6 exf2 timer 2 external flag set when a capture or a reload is caused by a negative transition on t2ex pin if exen2 = 1. when set, causes the cpu to vector to time r 2 interrupt routine when timer 2 interrupt is enabled. must be cleared by software. exf2 doesn?t cause an interrupt in up/down counter mode (dcen=1) 5 rclk receive clock bit for uart cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3. set to use timer 2 overflow as receive clock for serial port in mode 1 or 3. 4tclk transmit clock bit for uart cleared to use timer 1 overflow as transm it clock for serial port in mode 1 or 3. set to use timer 2 overflow as transmi t clock for serial port in mode 1 or 3. 3 exen2 timer 2 external enable bit cleared to ignore events on t2ex pin for timer 2 operation. set to cause a capture or reload when a negative transition on t2ex pin is detected, if timer 2 is not used to clock the serial port. 2tr2 timer 2 run control bit cleared to turn off timer 2. set to turn on timer 2. 1c/t2# timer/counter 2 select bit cleared for timer operation (input from internal clock system: f clk periph ). set for counter operation (input from t2 input pin, falling edge trigger). must be 0 for clock out mode. 0 cp/rl2# timer 2 capture/reload bit if rclk = 1 or tclk = 1, cp/rl2# is i gnored and timer is forced to auto-reload on timer 2 overflow. cleared to auto-reload on timer 2 overfl ows or negative transitions on t2ex pin if exen2 = 1. set to capture on negative transitions on t2ex pin if exen2 = 1.
43 4113d?8051?01/09 at80c51rd2 table 11-12. pcon register pcon - power contro l register (87h) reset value = 00x1 0000b not bit addressable power-off flag reset value will be 1 only after a power on (cold reset). a warm reset doesn?t affect the value of this bit. 76543210 smod1 smod0 - pof gf1 gf0 pd idl bit number bit mnemonic description 7smod1 serial port mode bit 1 for uart set to select double baud rate in mode 1, 2 or 3. 6smod0 serial port mode bit 0 for uart cleared to select sm0 bit in scon register. set to select fe bit in scon register. 5- reserved the value read from this bit is i ndeterminate. do not set this bit. 4pof power-off flag cleared to recognize next reset type. set by hardware when v cc rises from 0 to its nominal voltage. can also be set by software. 3gf1 general purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 2gf0 general purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 1pd power-down mode bit cleared by hardware when reset occurs. set to enter power-down mode. 0idl idle mode bit cleared by hardware when interrupt or reset occurs. set to enter idle mode.
44 4113d?8051?01/09 at80c51rd2 table 11-13. bdrcon register bdrcon - baud rate control register (9bh) reset value = xxx0 0000b not bit addressable 76543210 - - - brr tbck rbck spd src bit number bit mnemonic description 7- reserved the value read from this bit is i ndeterminate. do not set this bit 6- reserved the value read from this bit is i ndeterminate. do not set this bit 5- reserved the value read from this bit is i ndeterminate. do not set this bit. 4brr baud rate run control bit cleared to stop the internal baud rate generator. set to start the internal baud rate generator. 3tbck transmission baud rate generator selection bit for uart cleared to select timer 1 or timer 2 for the baud rate generator. set to select internal baud rate generator. 2rbck reception baud rate generator selection bit for uart cleared to select timer 1 or timer 2 for the baud rate generator. set to select internal baud rate generator. 1spd baud rate speed control bit for uart cleared to select the slow baud rate generator. set to select the fast baud rate generator. 0src baud rate source select bit in mode 0 for uart cleared to select f osc /12 as the baud rate generator (f clk periph /6 in x2 mode). set to select the internal baud rate generator for uarts in mode 0.
45 4113d?8051?01/09 at80c51rd2 12. interrupt system the at80c51rd2 have a total of 8 interrupt vectors: two external interrupts (int0 and int1 ), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, keyboard interrupt and the pca global interrupt. these interrupts are shown in figure 12-1. figure 12-1. interrupt control system each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the interrupt enable register ( table 12-5 and table 12-3 ). this register also contains a global disable bit, which must be cleared to disable all interrupts at once. each interrupt source also can be individually pr ogrammed to one out of four priority levels by setting or clearing a bit in the interrupt priority register ( table 12-6 ) and in the interrupt priority high register ( table 12-4 and table 12-5 ) shows the bit values and priority levels associated with each combination. 12.1 registers the pca interrupt vector is located at address 0033h, the keyboard interrupt vector is located at address 004bh. all other vectors addresses are the same as standard c52 devices. ie1 0 3 high priority interrupt interrupt polling sequence, decreasing from high to low priority low priority interrupt global disable individual enable exf2 tf2 ti ri tf0 int0 int1 tf1 iph, ipl ie0 0 3 0 3 0 3 0 3 0 3 0 3 pca it kbd it 0 3
46 4113d?8051?01/09 at80c51rd2 table 12-1. priority level bit values a low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-prior- ity interrupt. a high-priority interrupt can?t be interrupted by any other interrupt source. if two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. if interrupt requests of the same priority level are received simul- taneously, an internal polling sequence determine s which request is serv iced. thus within each priority level there is a second priority structure determ ined by the polling sequence. table 12-2. ieo register ie0 - interrupt enable register (a8h) iph.x ipl.x interrupt level priority 000 (lowest) 011 102 1 1 3 (highest) 76543210 ea ec et2 es et1 ex1 et0 ex0 bit number bit mnemonic description 7ea enable all interrupt bit cleared to disable all interrupts. set to enable all interrupts. 6ec pca interrupt enable bit cleared to disable. set to enable. 5et2 timer 2 overflow interrupt enable bit cleared to disable timer 2 overflow interrupt. set to enable timer 2 overflow interrupt. 4es serial port enable bit cleared to disable serial port interrupt. set to enable serial port interrupt. 3et1 timer 1 overflow interrupt enable bit cleared to disable timer 1 overflow interrupt. set to enable timer 1 overflow interrupt. 2 ex1 external interrupt 1 enable bit cleared to disable external interrupt 1. set to enable external interrupt 1. 1et0 timer 0 overflow interrupt enable bit cleared to disable timer 0 overflow interrupt. set to enable timer 0 overflow interrupt. 0 ex0 external interrupt 0 enable bit cleared to disable external interrupt 0. set to enable external interrupt 0.
47 4113d?8051?01/09 at80c51rd2 reset value = 0000 0000b bit addressable table 12-3. ipl0 register ipl0 - interrupt priority register (b8h) reset value = x000 0000b bit addressable table 12-4. iph0 register iph0 - interrupt priority high register (b7h) 76543210 - ppcl pt2l psl pt1l px1l pt0l px0l bit number bit mnemonic description 7- reserved the value read from this bit is i ndeterminate. do not set this bit. 6 ppcl pca interrupt priority bit refer to ppch for priority level. 5pt2l timer 2 overflow interrupt priority bit refer to pt2h for priority level. 4 psl serial port priority bit refer to psh for priority level. 3pt1l timer 1 overflow interrupt priority bit refer to pt1h for priority level. 2 px1l external interrupt 1 priority bit refer to px1h for priority level. 1pt0l timer 0 overflow interrupt priority bit refer to pt0h for priority level. 0 px0l external interrupt 0 priority bit refer to px0h for priority level. 76543210 - ppch pt2h psh pt1h px1h pt0h px0h
48 4113d?8051?01/09 at80c51rd2 reset value = x000 0000b not bit addressable table 12-5. ie1 register ie1 - interrupt enable register (b1h) bit number bit mnemonic description 7- reserved the value read from this bit is i ndeterminate. do not set this bit. 6 ppch pca interrupt priority high bit. ppch ppcl priority level 0 0lowest 01 10 1 1highest 5pt2h timer 2 overflow interrupt priority high bit pt2h pt2l priority level 0 0lowest 01 10 1 1highest 4 psh serial port priority high bit psh psl priority level 0 0lowest 0 1 1 0 1 1highest 3pt1h timer 1 overflow interrupt priority high bit pt1h pt1l priority level 00 lowest 01 10 11 highest 2 px1h external interrupt 1 priority high bit px1h px1l priority level 0 0lowest 01 10 1 1highest 1pt0h timer 0 overflow interrupt priority high bit pt0h pt0l priority level 0 0lowest 0 1 10 1 1highest 0 px0h external interrupt 0 priority high bit px0h px0l priority level 0 0lowest 01 10 1 1highest 76543210 -------kbd
49 4113d?8051?01/09 at80c51rd2 reset value = xxxx xxx0b bit addressable table 12-6. ipl1 register ipl1 - interrupt priority register (b2h) reset value = xxxx xxx0b bit addressable table 12-7. iph1 register bit number bit mnemonic description 7- reserved 6- reserved 5- reserved 4- reserved 3- reserved 2- reserved 1- reserved 0 kbd keyboard interrupt enable bit cleared to disable keyboard interrupt. set to enable keyboard interrupt. 76543210 -------kbdl bit number bit mnemonic description 7- reserved the value read from this bit is i ndeterminate. do not set this bit. 6- reserved the value read from this bit is i ndeterminate. do not set this bit. 5- reserved the value read from this bit is i ndeterminate. do not set this bit. 4- reserved the value read from this bit is i ndeterminate. do not set this bit. 3- reserved the value read from this bit is i ndeterminate. do not set this bit. 2- reserved the value read from this bit is i ndeterminate. do not set this bit. 1- reserved the value read from this bit is i ndeterminate. do not set this bit. 0 kbdl keyboard interrupt priority bit refer to kbdh for priority level.
50 4113d?8051?01/09 at80c51rd2 iph1 - interrupt priority high register (b3h) reset value = xxxx xxx0b not bit addressable 12.2 interrupt sources and vector addresses table 12-8. interrupt sources and vector addresses 76543210 ------- kbdh bit number bit mnemonic description 7- reserved the value read from this bit is i ndeterminate. do not set this bit. 6- reserved the value read from this bit is i ndeterminate. do not set this bit. 5- reserved the value read from this bit is i ndeterminate. do not set this bit. 4- reserved the value read from this bit is i ndeterminate. do not set this bit. 3- reserved the value read from this bit is i ndeterminate. do not set this bit. 2- reserved the value read from this bit is i ndeterminate. do not set this bit. 1- reserved the value read from this bit is i ndeterminate. do not set this bit. 0 kbdh keyboard interrupt priority high bit kb dh kbdl priority level 00 lowest 0 1 10 1 1 highest number polling priority interrupt source interrupt request vector address 0 0 reset 0000h 1 1 int0 ie0 0003h 2 2 timer 0 tf0 000bh 3 3 int1 ie1 0013h 4 4 timer 1 if1 001bh 5 6 uart ri+ti 0023h 6 7 timer 2 tf2+exf2 002bh 7 5 pca cf + ccfn (n = 0-4) 0033h 8 8 keyboard kbdit 003bh
51 4113d?8051?01/09 at80c51rd2
52 4113d?8051?01/09 at80c51rd2 13. keyboard interface the at80c51rd2 implement a keyboard interface allowing the connection of a 8 x n matrix key- board. it is based on 8 inputs with programmabl e interrupt capability on both high or low level. these inputs are available as alternate function of p1 and allow to exit from idle and power- down modes. the keyboard interfaces with the c51 core through 3 special function registers: kbls, the key- board level selection register (table 13-3), kbe, the keyboard interrupt enable register (table 13-2), and kbf, the keyboard flag register (table 13-1). 13.0.1 interrupt the keyboard inputs are considered as 8 independent interrupt sources sharing the same inter- rupt vector. an interrupt enable bit (kbd in ie1) allows global enable or disable of the keyboard interrupt (see figure 13-1). as detailed in figure 13-2 each key board input has the capability to detect a programmable level according to kbls.x bit value. level detection is then reported in interrupt flags kbf.x that can be ma sked by software using kbe.x bits. this structure allow keyboard arrangement from 1 x n to 8 x n matrix and allows usage of p1 inputs for other purpose. figure 13-1. keyboard interface block diagram figure 13-2. keyboard input circuitry 13.0.2 power reduction mode p1 inputs allow exit from idle and power-down modes as detailed in section ?power-down mode?, page 56. p1:x kbe.x kbf.x kbls.x 0 1 v cc internal pull-up p1.0 keyboard interface interrupt request kbd ie1 input circuitry p1.1 input circuitry p1.2 input circuitry p1.3 input circuitry p1.4 input circuitry p1.5 input circuitry p1.6 input circuitry p1.7 input circuitry kbdit
53 4113d?8051?01/09 at80c51rd2 13.1 registers table 13-1. kbf register kbf - keyboard flag register (9eh) reset value = 0000 0000b 76543210 kbf7 kbf6 kbf5 kbf4 kbf3 kbf2 kbf1 kbf0 bit number bit mnemonic description 7 kbf7 keyboard line 7 flag set by hardware when the port line 7 detects a programmed level. it generates a keyboard interrupt request if the kbkbie.7 bit in kbie register is set. must be cleared by software. 6 kbf6 keyboard line 6 flag set by hardware when the port line 6 detects a programmed level. it generates a keyboard interrupt request if the kbie.6 bit in kbie register is set. must be cleared by software. 5 kbf5 keyboard line 5 flag set by hardware when the port line 5 detects a programmed level. it generates a keyboard interrupt request if the kbie.5 bit in kbie register is set. must be cleared by software. 4 kbf4 keyboard line 4 flag set by hardware when the port line 4 detects a programmed level. it generates a keyboard interrupt request if the kbie.4 bit in kbie register is set. must be cleared by software. 3 kbf3 keyboard line 3 flag set by hardware when the port line 3 detects a programmed level. it generates a keyboard interrupt request if the kbie.3 bit in kbie register is set. must be cleared by software. 2 kbf2 keyboard line 2 flag set by hardware when the port line 2 detects a programmed level. it generates a keyboard interrupt request if the kbie.2 bit in kbie register is set. must be cleared by software. 1 kbf1 keyboard line 1 flag set by hardware when the port line 1 detects a programmed level. it generates a keyboard interrupt request if the kbie.1 bit in kbie register is set. must be cleared by software. 0 kbf0 keyboard line 0 flag set by hardware when the port line 0 detects a programmed level. it generates a keyboard interrupt request if the kbie.0 bit in kbie register is set. must be cleared by software.
54 4113d?8051?01/09 at80c51rd2 table 13-2. kbe register kbe - keyboard input enable register (9dh) reset value = 0000 0000b 76543210 kbe7 kbe6 kbe5 kbe4 kbe3 kbe2 kbe1 kbe0 bit number bit mnemonic description 7 kbe7 keyboard line 7 enable bit cleared to enable standard i/o pin. set to enable kbf.7 bit in kbf register to generate an interrupt request. 6 kbe6 keyboard line 6 enable bit cleared to enable standard i/o pin. set to enable kbf.6 bit in kbf register to generate an interrupt request. 5 kbe5 keyboard line 5 enable bit cleared to enable standard i/o pin. set to enable kbf.5 bit in kbf register to generate an interrupt request. 4 kbe4 keyboard line 4 enable bit cleared to enable standard i/o pin. set to enable kbf.4 bit in kbf register to generate an interrupt request. 3 kbe3 keyboard line 3 enable bit cleared to enable standard i/o pin. set to enable kbf.3 bit in kbf register to generate an interrupt request. 2 kbe2 keyboard line 2 enable bit cleared to enable standard i/o pin. set to enable kbf.2 bit in kbf register to generate an interrupt request. 1 kbe1 keyboard line 1 enable bit cleared to enable standard i/o pin. set to enable kbf.1 bit in kbf register to generate an interrupt request. 0 kbe0 keyboard line 0 enable bit cleared to enable standard i/o pin. set to enable kbf.0 bit in kbf register to generate an interrupt request.
55 4113d?8051?01/09 at80c51rd2 table 13-3. kbls register kbls - keyboard level select or register (9ch) reset value = 0000 0000b 76543210 kbls7 kbls6 kbls5 kbls4 kbls3 kbls2 kbls1 kbls0 bit number bit mnemonic description 7 kbls7 keyboard line 7 level selection bit cleared to enable a low level detection on port line 7. set to enable a high level detection on port line 7. 6 kbls6 keyboard line 6 level selection bit cleared to enable a low level detection on port line 6. set to enable a high level detection on port line 6. 5 kbls5 keyboard line 5 level selection bit cleared to enable a low level detection on port line 5. set to enable a high level detection on port line 5. 4 kbls4 keyboard line 4 level selection bit cleared to enable a low level detection on port line 4. set to enable a high level detection on port line 4. 3 kbls3 keyboard line 3 level selection bit cleared to enable a low level detection on port line 3. set to enable a high level detection on port line 3. 2 kbls2 keyboard line 2 level selection bit cleared to enable a low level detection on port line 2. set to enable a high level detection on port line 2. 1 kbls1 keyboard line 1 level selection bit cleared to enable a low level detection on port line 1. set to enable a high level detection on port line 1. 0 kbls0 keyboard line 0 level selection bit cleared to enable a low level detection on port line 0. set to enable a high level detection on port line 0.
56 4113d?8051?01/09 at80c51rd2 14. power management 14.1 idle mode an instruction that sets pcon.0 indicates that it is the last instruction to be executed before going into idle mode. in idle mode, the internal clock signal is gated off to the cpu, but not to the interrupt, timer, and serial port functions. the cpu status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator and all other registers maintain their data during idle. the port pins hold the logical states they had at the time idle was acti- vated. ale and psen hold at logic high level. there are two ways to terminate the idle mode. activation of any enabled interrupt will cause pcon.0 to be cleared by hardwa re, terminating the idle mode. the interrupt will be serviced, and following reti the next inst ruction to be execut ed will be the one following the instruction that put the device into idle. the flag bits gf0 and gf1 can be used to give an indication if an interrupt occurred during nor- mal operation or during idle. for example, an instruction that activates idle can also set one or both flag bits. when idle is terminated by an in terrupt, the interrupt service routine can examine the flag bits. the other way of terminating the idle mode is with a hardware rese t. since the clock oscillator is still running, the hardware reset needs to be held active for on ly two machine cycles (24 oscilla- tor periods) to complete the reset. 14.2 power-down mode to save maximum power, a power-down mode can be invoked by software (refer to table 11- 12 , pcon register). in power-down mode, the oscillator is stopped and the instruction that invoked power-down mode is the last instruction executed. the inte rnal ram and sfrs retain their value until the power-down mode is terminated. v cc can be lowered to save further power. either a hardware reset or an external interrupt can cause an exit from power-down. to properly terminate power- down, the reset or external interrupt should not be executed before v cc is restored to its normal operating level and must be held active long enough for the osc illator to restart and stabilize. only external interrupts int0 , int1 and keyboard interrupts are useful to exit from power-down. thus, the interrupt must be enabled and configured as level - or edge - sensitive interrupt input. when keyboard interrupt occurs after a power-down mode, 1024 clocks are necessary to exit to power-down mode and enter in operating mode. holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in figure 14-1 . when both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and powe r-down exit will be completed when the first input is released. in this case, the higher priority interrupt service rout ine is executed. once the interrupt is serviced, the next instruction to be executed after reti will be the one following the instruction that put at80c51rd2 into power-down mode.
57 4113d?8051?01/09 at80c51rd2 figure 14-1. power-down ex it waveform exit from power-down by reset redefines all the sfrs, exit from power-down by external inter- rupt does no affect the sfrs. exit from power-down by either reset or external interrupt does not affect the internal ram content. note: if idle mode is activated with power-down mode (idl and pd bits set), the exit sequence is unchanged, when execution is vectored to interrupt, pd and idl bits are cleared and idle mode is not entered. table 14-1 shows the state of ports during idle and power-down modes. note: 1. port 0 can force a 0 level. a "one" will leave port floating. int1 int0 xtal power-down phase oscillator restart active phase active phase table 14-1. state of ports mode program memory ale psen port0 port1 port2 port3 idle internal 1 1 port data (1) port data port data port data idle external 1 1 floating port data address port data power-down internal 0 0 port dat (1) port data port data port data power-down external 0 0 floating port data port data port data
58 4113d?8051?01/09 at80c51rd2 15. hardware watchdog timer the wdt is intended as a recovery method in situations where the cpu may be subjected to software upset. the wdt consists of a 14-bit counter and the watchdog timer reset (wdtrst) sfr. the wdt is by default disabled from exiting reset. to enable the wdt, user must write 01eh and 0e1h in sequence to the wdtrst, sfr location 0a6h. when wdt is enabled, it will increment every machine cycle while the oscillato r is running and there is no way to disable the wdt except through reset (either hardware reset or wdt overflow reset). when wdt overflows, it will drive an output reset high pulse at the rst-pin. 15.1 using the wdt to enable the wdt, user must write 01eh and 0e1h in sequence to the wdtrst, sfr loca- tion 0a6h. when wdt is enabled, the user needs to service it by writing to 01eh and 0e1h to wdtrst to avoid wdt overflow. the 14-bit c ounter overflows when it reaches 16383 (3fffh) and this will reset the device. when wdt is en abled, it will increment ev ery machine cycle while the oscillator is running. therefore, the user must reset the wdt at least every 16383 machine cycles. to reset the wdt the user must write 01eh and 0e1h to wdtrst. wdtrst is a write only register. the wdt counter cannot be re ad or written. when wdt overflows, it will generate an output reset pulse at the rst-pin. the reset pulse duration is 96 x t clk periph , where t clk periph = 1/f clk periph . to make the best use of the wdt, it should be serviced in those sec- tions of code that will periodically be executed within the time required to prevent a wdt reset. to have a more powerful wdt, a 2 7 counter has been added to ex tend the time-o ut capability, ranking from 16 ms to 2s @ f osc = 12 mhz. to manage this feature, refer to wdtprg register description, table 15-1 . table 15-1. wdtrst register wdtrst - watchdog reset register (0a6h) reset value = xxxx xxxxb write only, this sfr is used to reset/enable the wdt by writing 01eh then 0e1h in sequence. 76543210 --------
59 4113d?8051?01/09 at80c51rd2 table 15-2. wdtprg register wdtprg - watchdog timer out register (0a7h) reset value = xxxx x000 15.2 wdt during power-down and idle in power-down mode the oscillato r stops, which means the wdt also stops. while in power- down mode the user does not need to service the wdt. there are 2 methods of exiting power- down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering power-down mode. when power-down is exited with hardware reset, servicing the wdt should occur as normal, whenever the at 80c51rd2 is reset. exiting power-down with an interrupt is significantly differen t. the interrupt is he ld low long enough for the oscillato r to stabi- lize. when the interrupt is brought high, the interrupt is serviced. to prevent the wdt from resetting the device while the interrupt pin is held low, the wdt is not started until the interrupt is pulled high. it is suggested that the wdt be reset during the interrupt service routine. to ensure that the wdt does not overflow within a few states of exiting of power-down, it is bet- ter to reset the wdt just before entering power-down. in the idle mode, the oscillator continues to run. to prevent the wdt from resetting the at80c51rd2 while in idle mode, the user should always set up a timer that will periodically exit idle, service the wdt, and re-enter idle mode. 76543210 - - - - - s2 s1 s0 bit number bit mnemonic description 7- reserved the value read from this bit is undetermined. do not try to set this bit. 6- 5- 4- 3- 2s2 wdt time-out select bit 2 1s1 wdt time-out select bit 1 0s0 wdt time-out select bit 0 s2 s1 s0 selected time-out 00 0 (2 14 - 1) machine cycles, 16. 3 ms @ f osc =12 mhz 00 1 (2 15 - 1) machine cycles, 32.7 ms @ f osc =12 mhz 01 0 (2 16 - 1) machine cycles, 65. 5 ms @ f osc =12 mhz 01 1 (2 17 - 1) machine cycles, 131 ms @ f osc =12 mhz 10 0 (2 18 - 1) machine cycles, 262 ms @ f osc =12 mhz 10 1 (2 19 - 1) machine cycles, 542 ms @ f osc =12 mhz 11 0 (2 20 - 1) machine cycles, 1.05 s @ f osc =12 mhz 11 1 (2 21 - 1) machine cycles, 2.09 s @ f osc =12 mhz
60 4113d?8051?01/09 at80c51rd2 16. power-off flag the power-off flag allows the user to distinguish between a ?cold start? reset and a ?warm start? reset. a cold start reset is the one induced by v cc switch-on. a warm start reset occurs while v cc is still applied to the device and could be generated for example by an exit from power-down. the power-off flag (pof) is located in pcon register (table 16-1). pof is set by hardware when v cc rises from 0 to its nominal voltage. the pof can be set or cleared by software allow- ing the user to determine the type of reset. table 16-1. pcon register pcon - power contro l register (87h) reset value = 00x1 0000b not bit addressable 76543210 smod1 smod0 - pof gf1 gf0 pd idl bit number bit mnemonic description 7smod1 serial port mode bit 1 set to select double baud rate in mode 1, 2 or 3. 6smod0 serial port mode bit 0 cleared to select sm0 bit in scon register. set to select fe bit in scon register. 5- reserved the value read from this bit is i ndeterminate. do not set this bit. 4pof power-off flag cleared to recognize next reset type. set by hardware when v cc rises from 0 to its nominal voltage. can also be set by software. 3gf1 general purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 2gf0 general purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 1pd power-down mode bit cleared by hardware when reset occurs. set to enter power-down mode. 0idl idle mode bit cleared by hardware when interrupt or reset occurs. set to enter idle mode.
61 4113d?8051?01/09 at80c51rd2 17. reduced emi mode the ale signal is used to demultiplex address and data buses on port 0 when used with exter- nal program or data memory. nevertheless, during internal code execution, ale signal is still generated. in order to reduce emi, ale signal can be disabled by setting ao bit. the ao bit is located in auxr register at bit loca tion 0. as soon as ao is set, ale is no longer output but remains active during movx and movc instructions and external fetches. during ale disabling, ale pin is weakly pulled high. table 17-1. auxr register auxr - auxiliary register (8eh) 76543210 - - m0 - xrs1 xrs0 extram ao bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit 6- reserved the value read from this bit is in determinate. do not set this bit 5m0 pulse length cleared to stretch movx control: the rd and the wr pulse length is 6 clock periods (default). set to stretch movx control: the rd and the wr pulse length is 30 clock periods. 4- reserved the value read from this bit is in determinate. do not set this bit 3xrs1 xram size xrs1 xrs0 xram size 0 0256 bytes (default) 0 1512 bytes 1 0768 bytes 1 11024 bytes 2xrs0 1 extram extram bit cleared to access internal xr am using movx @ ri/ @ dptr. set to access external memory. programmed by hardware after power-up regarding hardware security byte (hsb), default setting, xram selected. 0ao ale output bit cleared, ale is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if x2 mode is used) (default). set, ale is active only during a movx or movc instructione is used.
62 4113d?8051?01/09 at80c51rd2
60 4113d?8051?01/09 at80c51rd2 17. e lectrical characteristics 17.1 dc parameters for standard voltage t a = 0 c to +70 c; v ss = 0v; v cc = 4.5v to 5.5v; f = 10 to 40 mhz t a = -40 c to +85 c; v ss = 0v; v cc =4.5v to 5.5v; f = 10 to 40 mhz table 17-1. absolute maximum ratings c = commercial......................................................0 c to 70 c i = industrial ......... .............. .............. .............. .....-40 c to 85 c storage temperature .................................... -65 c to + 150 c voltage on v cc to v ss (standard voltage) .........-0.5v to + 6.5v voltage on v cc to v ss (low voltage)..................-0.5v to + 4.5v voltage on any pin to v ss ..........................-0.5v to v cc + 0.5v power dissipation .............................................................. 1 w note: stresses at or above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. exposure to abso- lute maximum rating conditions may affect device reliability. power dissipation value is based on the maximum allowable die temperature and the thermal resistance of the package. symbol parameter min typ max unit test conditions v il input low voltage -0.5 0.2 v cc - 0.1 v v ih input high voltage except rst, xtal1 0.2 v cc + 0.9 v cc + 0.5 v v ih1 input high voltage rst, xtal1 0.7 v cc v cc + 0.5 v v ol output low voltage, ports 1, 2, 3, 4 (6) 0.3 0.45 1.0 v v v i ol = 100 a (4) i ol = 1.6 ma (4) i ol = 3.5 ma (4) v ol1 output low voltage, port 0, ale, psen (6) 0.3 0.45 1.0 v v v i ol = 200 a (4) i ol = 3.2 ma (4) i ol = 7.0 ma (4) v oh output high voltage, ports 1, 2, 3, 4 v cc - 0.3 v cc - 0.7 v cc - 1.5 v v v i oh = -10 a i oh = -30 a i oh = -60 a v cc = 5v 10% v oh1 output high voltage, port 0, ale, psen v cc - 0.3 v cc - 0.7 v cc - 1.5 v v v i oh = -200 a i oh = -3.2 ma i oh = -7.0 ma v cc = 5v 10% r rst rst pull-down resistor 50 200 (5) 250 k i il logical 0 input current ports 1, 2, 3, 4 and 5 -50 av in = 0.45v i li input leakage current 10 a 0.45v < v in < v cc i tl logical 1 to 0 transition current, ports 1, 2, 3, 4 -650 av in = 2.0 v c io capacitance of i/o buffer 10 pf fc = 3 mhz t a = 25 c i pd power-down current 100 150 a4.5v < v cc < 5.5v (3) i ccop power supply current on normal mode 0.29 x frequency (mhz) + 4 ma v cc = 5.5v (1) i ccidle power supply current on idle mode 0.16 x frequency (mhz) + 4 ma v cc = 5.5v (2)
61 4113d?8051?01/09 at80c51rd2 17.2 dc parameters for standard voltage (2) t a = 0 c to +70 c; v ss = 0 v; v cc = 2.7v to 5.5v; f = 10 to 40 mhz t a = -40 c to +85 c; v ss = 0 v; v cc = 2.7v to 5.5v; f = 10 to 40 mhz notes: 1. operating i cc is measured with all output pins disconnected; xtal1 driven with t clch , t chcl = 5 ns (see figure 17-4.), v il = v ss + 0.5v, v ih = v cc - 0.5v; xtal2 n.c.; ea = rst = port 0 = v cc . i cc would be slightly higher if a crystal oscillator used (see figure 17-1 ). 2. idle i cc is measured with all output pins disconnected; xtal1 driven with t clch , t chcl = 5 ns, v il = v ss + 0.5v, v ih = v cc - 0.5v; xtal2 n.c; port 0 = v cc ; ea = rst = v ss (see figure 17-2 ). 3. power-down i cc is measured with all output pins disconnected; ea = v ss , port 0 = v cc ; xtal2 nc.; rst = v ss (see figure 17-3 ). 4. capacitance loading on ports 0 and 2 may cause spur ious noise pulses to be superimposed on the v ol s of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions during bus operation. in the worst cases (capacit ive loading 100pf), the noise pulse on the ale line may exceed 0.45v with maxi v ol peak 0.6v. a schmitt trigger use is not necessary. 5. typical are based on a limited number of samples and are no t guaranteed. the values listed are at room temperature and 5v. 6. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma maximum i ol per 8-bit port: port 0: 26 ma ports 1, 2 and 3: 15 ma maximum total i ol for all output pins: 71 ma if i ol exceeds the test condition, v ol may exceed the related specification. pi ns are not guaranteed to sink current greater than the listed test conditions. 7. for other values, please contact your sales office. symbol parameter min typ (5) max unit test conditions v il input low voltage -0.5 0.2 v cc - 0.1 v v ih input high voltage except xtal1, rst 0.2 v cc + 0.9 v cc + 0.5 v v ih1 input high voltage, xtal1, rst 0.7 v cc v cc + 0.5 v v ol output low voltage, ports 1, 2, 3, 4 and 5 (6) 0.45 v i ol = 0.8 ma (4) v ol1 output low voltage, port 0, ale, psen (6) 0.45 v i ol = 1.6 ma (4) v oh output high voltage, ports 1, 2, 3, 4 and 5 0.9 v cc vi oh = -10 a v oh1 output high voltage, port 0, ale, psen 0.9 v cc vi oh = -40 a i il logical 0 input current ports 1, 2, 3, 4 and 5 -50 av in = 0.45v i li input leakage current 10 a 0.45v < v in < v cc i tl logical 1 to 0 transition current, ports 1, 2, 3, 4 and 5 -650 av in = 2.0v r rst rst pulldown resistor 50 200 250 k cio capacitance of i/o buffer 10 pf fc = 3 mhz t a = 25 c i pd power-down current 120 150 av cc =2.7v to 5.5v (3) i ccop power supply current on normal mode 0.29 x frequency (mhz) + 4 ma v cc = 5.5v (1) i ccidle power supply current on idle mode 0.16 x frequency (mhz) + 4 ma v cc = 5.5v (2)
62 4113d?8051?01/09 at80c51rd2 figure 17-1. i cc test condition, active mode figure 17-2. i cc test condition, idle mode figure 17-3. i cc test condition, power-down mode ea v cc v cc i cc (nc) clock signal v cc all other pins are disconnected. rst xtal2 xtal1 v ss v cc p0 rst ea xtal2 xtal1 v ss v cc v cc i cc (nc) p0 v cc all other pins are disconnected. clock signal rst ea xtal2 xtal1 v ss v cc v cc i cc (nc) p0 v cc all other pins are disconnected.
63 4113d?8051?01/09 at80c51rd2 figure 17-4. clock signal waveform for i cc tests in active and idle modes 17.3 ac parameters 17.3.1 explanation of the ac symbols each timing symbol has 5 characte rs. the first character is always a ?t? (stands for time). the other characters, depending on their positions, st and for the name of a signal or the logical sta- tus of that signal. the following is a list of all the characters and what they stand for. example:t avll = time for address valid to ale low. t llpl = time for ale low to psen low. (load capacitance fo r port 0, ale and psen = 100 pf; load capacitance for all other outputs = 80 pf.) table 17-2 table 17-5, and table 17-7 give the description of each ac symbols. table 17-4, table 17-6 and table 17-8 give for each range the ac parameter. table 17-3, table 17-4 and table 17-9 gives the frequency derating formula of the ac parame- ter for each speed range description. to calcul ate each ac symbols. ta ke the x value in the correponding column and use this value in the formula. example: t lliu for 20 mhz, standard clock. x = 35 ns t = 50 ns t cciv = 4t - x = 165 ns v cc -0.5v 0.45v 0.7v cc 0.2v cc -0.1 t clch t chcl t clch = t chcl = 5ns.
64 4113d?8051?01/09 at80c51rd2 17.3.2 external program memory characteristics table 17-2. symbol description table 17-3. ac parameters for a fix clock symbol parameter t oscillator clock period t lhll ale pulse width t avll address valid to ale t llax address hold after ale t lliv ale to valid instruction in t llpl ale to psen t plph psen pulse width t pliv psen to valid instruction in t pxix input instruction hold after psen t pxiz input instruction floatafter psen t aviv address to valid instruction in t plaz psen low to address float symbol -m units min max t25 ns t lhll 35 ns t avll 5ns t llax 5ns t lliv 65 ns t llpl 5ns t plph 50 ns t pliv 30 ns t pxix 0ns t pxiz 10 ns t aviv 80 ns t plaz 10 ns
65 4113d?8051?01/09 at80c51rd2 table 17-4. ac parameters for a variable clock 17.3.3 external program memory read cycle 17.3.4 external data memory characteristics symbol type standard clock x2 clock x parameter for - m range units t lhll min 2 t - x t - x 15 ns t avll min t - x 0.5 t - x 20 ns t llax min t - x 0.5 t - x 20 ns t lliv max 4 t - x 2 t - x 35 ns t llpl min t - x 0.5 t - x 15 ns t plph min 3 t - x 1.5 t - x 25 ns t pliv max 3 t - x 1.5 t - x 45 ns t pxix min x x 0 ns t pxiz max t - x 0.5 t - x 15 ns t aviv max 5 t - x 2.5 t - x 45 ns t plaz max x x 10 ns t pliv tplaz ale psen port 0 port 2 a0-a7 a0-a7 instr in instr in instr in address or sfr-p2 address a8-a15 address a8 - a15 12 t clcl t aviv t lhll t avll t lliv t llpl t plph t pxav t pxix t pxiz t llax
66 4113d?8051?01/09 at80c51rd2 table 17-5. symbol description table 17-6. ac parameters for a fix clock symbol parameter t rlrh rd pulse width t wlwh wr pulse width t rldv rd to valid data in t rhdx data hold after rd t rhdz data float after rd t lldv ale to valid data in t avdv address to valid data in t llwl ale to wr or rd t avwl address to wr or rd t qvwx data valid to wr transition t qvwh data set-up to wr high t whqx data hold after wr t rlaz rd low to address float t whlh rd or wr high to ale high symbol -m units min max t rlrh 125 ns t wlwh 125 ns t rldv 95 ns t rhdx 0ns t rhdz 25 ns t lldv 155 ns t avdv 160 ns t llwl 45 105 ns t avwl 70 ns t qvwx 5ns t qvwh 155 ns t whqx 10 ns t rlaz 0ns t whlh 545ns
67 4113d?8051?01/09 at80c51rd2 17.3.5 external data memory write cycle symbol type standard clock x2 clock x parameter for - m range units t rlrh min 6 t - x 3 t - x 25 ns t wlwh min 6 t - x 3 t - x 25 ns t rldv max 5 t - x 2.5 t - x 30 ns t rhdx min x x 0 ns t rhdz max 2 t - x t - x 25 ns t lldv max 8 t - x 4t -x 45 ns t avdv max 9 t - x 4.5 t - x 65 ns t llwl min 3 t - x 1.5 t - x 30 ns t llwl max 3 t + x 1.5 t + x 30 ns t avwl min 4 t - x 2 t - x 30 ns t qvwx min t - x 0.5 t - x 20 ns t qvwh min 7 t - x 3.5 t - x 20 ns t whqx min t - x 0.5 t - x 15 ns t rlaz max x x 0 ns t whlh min t - x 0.5 t - x 20 ns t whlh max t + x 0.5 t + x 20 ns t qvwh t llax ale psen wr port 0 port 2 a0-a7 data out address or sfr-p2 t avwl t llwl t qvwx address a8 - a15 or sfr p2 t whqx t whlh t wlwh
68 4113d?8051?01/09 at80c51rd2 17.3.6 external data memory read cycle 17.3.7 serial port timing - shift register mode table 17-7. symbol description table 17-8. ac parameters for a fix clock ale psen rd port 0 port 2 a0-a7 data in address or sfr-p2 t avwl t llwl t rlaz address a8-a15 or sfr p2 t rhdz t whlh t rlrh t lldv t rhdx t llax t avdv symbol parameter t xlxl serial port clock cycle time t qvhx output data set-up to clock rising edge t xhqx output data hold after clock rising edge t xhdx input data hold after clock rising edge t xhdv clock rising edge to input data valid symbol -m units min max t xlxl 300 ns t qvhx 200 ns t xhqx 30 ns t xhdx 0ns t xhdv 117 ns
69 4113d?8051?01/09 at80c51rd2 table 17-9. ac parameters for a variable clock 17.3.8 shift register timing waveforms 17.3.9 external clock drive waveforms 17.3.10 ac testing input/output waveforms ac inputs during testing are driven at v cc - 0.5 for a logic ?1? and 0.45v for a logic ?0?. timing measurement are made at v ih min for a logic ?1? and v il max for a logic ?0?. symbol type standard clock x2 clock x parameter for - m range units t xlxl min 12 t 6 t ns t qvhx min 10 t - x 5 t - x 50 ns t xhqx min 2 t - x t - x 20 ns t xhdx min x x 0 ns t xhdv max 10 t - x 5 t- x 133 ns input data valid valid valid valid 0123456 8 7 ale clock output data write to sbuf clear ri t xlxl t qvxh t xhqx t xhdv t xhdx set ti set ri instruction 01234567 valid valid valid valid v cc -0.5v 0.45v 0.7v cc 0.2v cc -0.1 t chcl t clcx t clcl t clch t chcx input/output 0.2 v cc + 0.9 0.2 v cc - 0.1 v cc -0.5v 0.45v
70 4113d?8051?01/09 at80c51rd2 17.3.11 float waveforms for timing purposes as port pin is no longer floating when a 100 mv changes from load voltage occurs and begins to float when a 100 mv change from the loaded v oh /v ol level occurs. i ol /i oh 20 ma. 17.3.12 clock waveforms valid in normal clock mode. in x2 mode xtal2 must be changed to xtal2/2. float v oh - 0.1 v v ol + 0.1 v v load v load + 0.1 v v load - 0.1 v
71 4113d?8051?01/09 at80c51rd2 figure 17-5. internal clock signals this diagram indicates when signals are clocked internally. the time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. this propagation delay is dependen t on variables such as temperature and pin loading. propa- gation also varies from output to output and component. typically though (t a = 25 c fully loaded) rd and wr propagation delays are approximately 50 ns. the other signals are typica lly 85 ns. propagation delays are incorporated in the ac specifications. p2 p2 data pcl out data pcl out data pcl out sampled sampled sampled state4 state5 state6 state1 state2 state3 state4 state5 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 float float float these signals are not activated during the execution of a movx instruction indicates address transitions external program memory fetch float data sampled dpl or rt out indicates dph or p2 sfr to pch transition pcl out (if program memory is external) pcl out (even if program memory is internal) pcl out (if program memory is external) old data new data p0 pins sampled p1, p2, p3 pins sampled p1, p2, p3 pins sampled p0 pins sampled rxd sampled internal clock xtal2 ale psen p0 p2 (ext) read cycle write cycle rd p0 wr port operation mov port src mov dest p0 mov dest port (p1. p2. p3) (includes into. int1. to t1) serial port shift clock txd (mode 0) data out dpl or rt out indicates dph or p2 sfr to pch transition p0 rxd sampled
63 4113d?8051?01/09 at80c51rd2 18. ordering information table 18-1. ordering information part number package temperature range packing at80c51rd2-3csum pdil40 industrial & green stick at80c51rd2-slsum plcc44 industrial & green stick at80c51rd2-rltum vqfp44 industrial & green tray AT80C51RD2-SLRUM plcc44 industrial & green tape & reel at80c51rd2-rlrum vqfp44 industrial & green tape & reel
64 4113d?8051?01/09 at80c51rd2 19. package information 19.1 pdil40
65 4113d?8051?01/09 at80c51rd2 19.2 plcc44
66 4113d?8051?01/09 at80c51rd2 st and ard no tes for plcc 1/ controlling dimensions : inches 2/ dimensioning and tolerancing per ansi y 14.5m - 1982. 3/ "d" and "e1" dimensions do not include mold flash or protusions. mold flash or protusions shall not exceed 0.20 mm (.008 inch) per side.
67 4113d?8051?01/09 at80c51rd2 19.3 vqfp44
68 4113d?8051?01/09 at80c51rd2 st and ard no tes for pqfp / vqfp / tqfp / dqfp 1/ controlling dimensions : inches 2/ all dimensioning and tolerancing conform to ansi y 14.5m - 1982. 3/ "d1 and e1" dimensions do not include mold protusions. mold protusions shall not exceed 0.25 mm (0.010 inch). the top package body size may be smaller than the bottom package body size by as much as 0.15 mm. 4/ datum plane "h" located at mold parting line and coincident with lead, where lead exits plastic body at bottom of parting line. 5/ datum "a" and "d" to be determined at datum plane h. 6/ dimension " f " does not include dambar protusion allowable dambar protusion shall be 0.08mm/.003" total in excess of the " f " dimension at maximum material condition . dambar cannot be located on the lower radius or the foot.
69 4113d?8051?01/09 at80c51rd2 20. datasheet change log 20.1 changes from 4113a - 09/02 to 4113b -03/05 1. added green product ordering information. 20.2 changes from 4113b -0 3/05 to 4113c -01/08 1. removed at80c51rd2 product offering table 18-1 on page 63 . 2. updated package drawings. 20.3 changes from 4113c -0 1/08 to 4113d -01/09 1. removed at83c51rd2 product offering

▲Up To Search▲

Price & Availability of AT80C51RD2-SLRUM

	To Download AT80C51RD2-SLRUM Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .